1. Field
The disclosure relates generally to an improved data processing system and more specifically to a method, computer program product, and apparatus for improved cache management. Still more particularly, the illustrative embodiments provide a method, apparatus, and computer program product for managing a number of cache lines in a cache.
2. Description of the Related Art
A cache is used by a processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory. The cache stores copies of the data from the most frequently used main memory locations. When the processing unit wishes to read or write a location in main memory, the processing unit first checks whether that memory location is in the cache. One way the check is performed is to compare the memory address sought by the operation being performed by the processing unit with the memory addresses available in the parts of the cache that may contain the data at the desired memory address.
For example, if the desired memory address is found in the cache, finding the desired memory address is referred to as a cache hit. The data at the corresponding cache location is transferred to the processing unit for immediate use, and the processing unit does not need to wait for the slower main memory to transmit the data at the requested memory address.
However, in the event the desired memory address is not presently stored in the cache, it is referred to as a cache miss. The data must be transferred from main memory to the processing unit using a memory bus prior to use. The data transferred from memory is typically stored in the cache, once transferred from main memory, for future use by the processing unit. Since the cache is smaller than main memory, only a portion of the memory addresses within main memory may be stored in the cache at a particular point in time. When the cache is full and data is transferred from main memory, an entry, or cache line, in the cache must be overwritten. If the cache line has been changed by an operation of the processor unit since being loaded into the cache from main memory, it is referred to as dirty. To prevent data loss, a dirty cache line is written to main memory prior to being overwritten by a new cache line. The method of selecting the cache line to be overwritten is referred to as a cache replacement scheme.
In times of heavy system utilization, a large number of cache lines may be replaced, or evicted, by incoming data from main memory. Some of the cache lines to be overwritten may be dirty. Performance is degraded by standard cache replacement schemes that write the dirty cache lines back to main memory during the time of heavy utilization. The memory bus, which is already transferring the large number of main memory read requests as a result of the heavy system utilization, also transfers the write requests generated by the cache evictions.